The LMS algorithm and SERDES receiver adaptation

23 Maggio 2024
Share on facebook Share on twitter
667
VIEW

Aula F3 Polo "E.Vitale" (Ex Etruria)
Scuola di Ingegneria
Pisa

e Online on Teams [Link]

 

Abstract

High speed data communication represents the backbone of our digital society. Every bit that is moved around the Internet goes through several optical and electrical channels that exploit serializer-deserializer interfaces (SERDES) at their core – Ethernet is based on serial communication. In addition to this, every current electronic device includes some SERDES, e.g., smartphones, USB devices, HDMI, PCI express, to mention but a few. Transmission speeds are approaching 224 Gb/s per lane, creating several challenges to designers, from electromagnetic issues all the way to software. In this talk, we will introduce fundamentals of Digital Signal Processing (DSP) based receiver architectures, which include a very demanding analog front end (AFE), and a high-performance digital processing core. We will focus on a fundamental algorithm that is at the base of receiver adaptation, the Least Mean Squares algorithm (LMS). Starting from a general problem formulation, we will derive the LMS algorithm, analyze its behavior and show with several examples how broad its applicability range is, which explains why the LMS is such a fundamental algorithm. We will then see how this solution is implemented in modern DSP, and what kind of tradeoffs need to be taken to achieve an efficient silicon implementation.

 

Bio

Fernando De Bernardinis received the Laurea degree in electrical engineering from the University of Pisa, Scuola S. Anna, Italy, in 1996, a Ph.D in Electrical Engineering from the same University in 2000, and M.S. and Ph.D. degrees from the University of California, Berkeley, in 2001 and 2005, respectively. He was Assistant Professor in the Department of Information Engineering at the University of Pisa until he joined Marvell Italy in 2006, where he still works after a series of acquisitions (eSilicon in 2017, Inphi in 2019, and Marvell in 2021). His research interests include architecture design and DSP algorithm optimization, digitally assisted analog design, mixed signal system level design. Since 2012, he has been leading the architecture and algorithm design of DSP based serial links. He is the author/coauthor of several international patents and publications.